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STA1052
DSP/MCU system for CD-DA, CD-CA, CD-ROM player
Data Brief
Features

CD-R, CD-RW playback Audio decoding (MP3,WMA,AAC) CLV (1x, 2x, 4x) and CAV mode (6x) On-chip USB-OTG host full speed 3.3 V 5 % operating supply range for I/O 1.8 V 5 % operating supply range for logic IDLE, WFI and STOP modes Power on reset / Brownout controller 33.8688 MHz external quartz/resonator Operating temperature range: -40 C to +85 C
LQFP144 (20x20x1.4 mm)
Acquisition

Full range adjustment-free digital PLL EFM demodulation and synchronization Q subcode and CD text decoder
Error correction

Embedded ARM7TDMI microcontroller

CIRC, capable of dual C1, quad C2 erasure RSPC capable of C3 corrections Jitter absorbing capacity 24 frames (CLV)
32 bit MCU with 3-stage pipeline @ 67 MHz 384 KB internal ROM (4 Mb on package RAM for development version) and 128 KB RAM I C master/slave (400 kHz) + 1 CRQ line Two high-speed UART full-duplex Two buffered SPI master/slave interface
2
Shock-proof controller

Up to 64 Mbit external SDRAM interface 8/16 bit data bus interface ADPCM (4:1) lossy compression for extended shock proof capability
Analog Front-end part

A, B, C, D, E, F voltage inputs Automatic gain and offset control ALPC circuit with integrated Power MOS 8 bit 2 channels general purpose ADC
Audio features

Two I2S transmitters and one I2S receiver SPDIF transmitter (IEC958) and receiver Sample-rate conversion from 8 kHz - 48 kHz input to 44.1 kHz output Digital equalizer for bass/treble control Built-in stereo DAC
Digital servo

Automatic fine gain/balance/offset adjustment for tracking and focus Embedded 16 bit servo DSP (33.8688 MHz) PDM controls for focus, tracking, spindle, sledge Embedded stepping sledge motor controller CLV & CAV spindle control
Development environment
5 pin JTAG port (IEEE 1149.1 standard) Device summary
Package LQFP144 Packing Tray
Table 1.
Order code STA1052S1
March 2008
Rev 1
1/14
www.st.com 14
For further information contact your local STMicroelectronics sales office.
Contents
STA1052
Contents
1 2 3 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 System block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3.1 3.2 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pin function description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
4 5
Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
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STA1052
Description
1
Description
The STA1052 is a single chip device which performs all functions related to read back of optical disk: servo control operations, reading optical disc decoding the High frequency signals, EFM decoding, error correction, software decoding of MP3 and WMA encoded audio, sample rate conversion, managing file system, serial transfer of audio/program through I2S/SPDIF, direct playback of audio through in-built audio DAC. It also performs software decoding of MP3, AAC and WMA encoded audio from USB or SD cardTM memory supports. Commands can be exchanged with the Host MCU either via one I2C port or two SPI ports. STA1052 chip comes along a broad software suite that comprehends different types of compressed audio files, File System Management, Play Lists. The key Media and File Types supported are briefly reported below:

Ability to play any USB/SD card compatible solid state memory media MPEG1-Layer 2 compressed audio files Playback of MP3 compressed audio files (all bit rates and VBR) Playback of lower bit rate MPEG2 layer 3 files and MPEG-2.5 extension Playback of WMA version 9 compressed audio files Playback of iTunes AAC compressed audio files Sample rate converter for recorded sampling rates other than 44.1kHz Support FAT16/FAT32 file systems Support ISO9660 and Joliet file systems
The software can manage the following File Information: folder and file names. ID3 tag information - as per versions 1.0-1.1, 2.0 - 2.4- is reported. Further parameters made available by ST software are: File type (i.e. .mp3, .wav, .wma, .cda, .aac), Bit rate, entire file path for current track and track elapsed time. STA1052 software provides the essential Navigation Commands: Previous/Next , Fast forward/Rewind, Jump to any file, Scan, Pause. All these commands can be programmed and configured via Command Protocol Interface. Two different types of Playlists are supported: Playlists with .pls extension, Playlists with .m3u extension. Robust software architecture provides an efficient error handling and related messaging. ST developed a software architecture that allows the patching of a few parts of software resident in ROM. Software patches are loaded into a very inexpensive serial Flash which provides the capability to patch up to 40 KByte of ROM software. Software build (patching) upgrade from media USB and SD card and from host MCU onto serial Flash is supported. STA1052 is intended for use in automotive entertainment system.
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2
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System block diagram
Figure 1.
SDRAM Interface
MD
digital equalizer Sync protection & EFM demodulator Sub code decoder Cross Interleaving Reed-Solomon
Digital PLL
Output interface
LD
Laser control
ADPCM Encoder
ADPCM Decoder
CLV buffer
DeScram + RSPC Frame Org
fade/ mute/ deemph
ADC1
AHB ITF
STA1052 block diagram
SPDIF-SONYLSI-I2S
ADC2
AUX ADC
System block diagram
master clock
+
A+C B+D E F TrackCount A+C 1.7Kx32 PRAM 256x16 XRAM 256x16 YRAM
A B C D E F
I/V OFFSET GAIN ADC
DSP
DECIM.
JumpSpeed TE FE defect
ARM Subsystem
B+D
+ RATE
E DAC ANALOG filter F
Track Loop filter Focus Loop filter SLED Loop filter
PLL
PDM/ stepper
Spindle Motor Feedback (CAV)
Focus Actuator Track Actuator Sled Motor Spindle Motor Ext Mem External Interrupt Obs/Debug
Application interface
AUDIO L/R out
Figure 1 provides the complete system block diagram, where the ARM sub-system is represented as a hierarchical block.
Quartz/ Ceramic
STA1052
STA1052
Pin description
3
3.1
Pin description
Pin connection
Figure 2. LQFP144 pin configuration (top view)
VDD3_Core1 DRCLKE DRRAS DRCAS DRCLK DRBA0 DRBA1 DRD10 DRD11 DRD12 DRD13 DRD14 DRD15 GPB11 GPB10 DRA10 DRA11 JTRST DRWR GPB9 DRA0 DRA1 DRA2 DRA3 DRA4 VDD3 DRA5 DRA6 DRA7 DRA8 DRA9 JTCK VDD
VSS
VSS
144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 DRD9 DRD8 GPB12 GPB13 GPB14 GPB15 DRD7 DRD6 DRD5 VDD VSS VDD3 DRD4 DRD3 DRD2 DRD1 DRD0 PLL_VSS18P PLL_VDDA33P PLL_XTI PLL_XTO PLL_VDDA18P PLL_VDD18P FE_VSSA33S FE_A FE_C FE_B FE_D FE_E FE_F FE_VDDA33S FE_VDDPAD1 FE_ADCIN1 FE_ADCIN2 FE_VREF_ADC FE_VREF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 FE_VSSA33R FE_MD_LAS FE_CAP_LAS FE_VDDPAD2 FE_TESTP FE_TESTN FE_VSSA33T FE_VSSA18AD VSS RESETN TESTEN REFFSR VSS FE_VDDA33R FE_CEXT FE_REXT FE_LD_LAS FE_LD1_LAS FE_VDDA33T FE_VDDA18AD SLED1 SLED2 GPA9 FFSR SPDL VDD VDD3 TFSR CAV LRCK GPA10 GPA11 GPA12 SDO BCLK GPA0 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 OUTR ADAC_REF1 VCM ADAC_REF2 OUTL ADAC_VDDA ADAC_VSSA VSS VDD3 JTMS JTDO JTDI GPB7 GPB6 VDD GPB8 GPB5 GPB4 GPB3 GPB2 GPB1 VDD3_Core2 VSS GPB0 GPA8 GPA7 GPA6 GPA5 GPA4 GPA13 GPA3 GPA2 GPA1 NC NC NC
NC
AC00563
1. NC defines not connected pins.
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Pin description
STA1052
3.2
Pin function description
This pin list contains the definition and description of all pins. Table 2 gives pin list for LQFP144.
Table 2.
N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
Pin List
Name Description GPIO PC9 (SDRAM data 9) GPIO PC8 (SDRAM data 8) GPIO PB12(BSPI1_SS) GPIO PB13 (BSPI1_MISO) GPIO PB14 (BSPI1_MOSI) GPIO PB15 (BSPI1_SCK) GPIO PC7 (SDRAM data 7) GPIO PC6 (SDRAM data 6) GPIO PC5 (SDRAM data 5) Core VDD1.8 V Digital pad ring VSS ground Digital pad ring VDD3 3.3 V GPIO PC4 (SDRAM data 4) GPIO PC3 (SDRAM data 3) GPIO PC2 (SDRAM data 2 or serial flash master in/slave out) GPIO PC1 (SDRAM Data 1 or serial flash master out/slave in) GPIO PC0 (SDRAM data 0 or serial Flash clock) PLL digital & analog ground PLL 3.3 analog power supply Crystal input Crystal output PLL 1.8V analog power supply PLL 1.8V digital power supply Ground for servo channels OPU A input OPU C input Pin type bidir, 3.3V , 4 mA bidir, 3.3 V, 4 mA bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 V, 4 mA bidir, 3.3 V, 4 mA bidir, 3.3 V, 4 mA VDD VSS VDD3 bidir, 3.3 V, 4 mA bidir, 3.3 V, 4 mA bidir, 3.3 V, 4 mA bidir, 3.3 V, 4 mA bidir, 3.3 V, 4 mA VSS VDD analog in analog out VDD VDD VSS analog in analog in LQFP144 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26
GPC9(DRD9) GPC8(DRD8) GPB12 GPB13 GPB14 GPB15 GPC7(DRD7) GPC6(DRD6) GPC5(DRD5) VDD VSS VDD3 GPC4(DRD4) GPC3(DRD3) GPC2(DRD2/ SFLASH_MISO) GPC1(DRD1/ SFLASH_MOSI) GPC0(DRD0/ SFLASH_SCK) PLL_VSS18P PLL_VDDA33P PLL_XTI PLL_XTO PLL_VDDA18P PLL_VDD18P FE_VSSA33S FE_A FE_C
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STA1052 Table 2.
N 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 FE_B FE_D FE_E FE_F FE_VDDA33S FE_VDDPAD1 FE_ADCIN1 FE_ADCIN2 FE_VREF_ADC FE_VREF FE_VDDA33R FE_CEXT FE_REXT FE_VSSA33R FE_MD_LAS FE_CAP_LAS FE_LD_LAS FE_LD1_LAS FE_VDDPAD2 FE_VDDA33T FE_TESTP FE_TESTN FE_VSSA33T FE_VDDA18AD FE_VSSA18AD VSS RESETN TESTEN FFSR REFFSR
Pin description Pin List (continued)
Name OPU B input OPU D input OPU E input OPU F input 3.3 V analog for servo channels/ 3.3 V for AFE pad ring (decoupling cap to Vssa) 3.3V for AFE pad ring General purpose ADC input 1 General purpose ADC input 2 General purpose ADC Vtop reference output External Vref pickup (decoupling cap 1 nF) Analog 3.3 V for bandgap External cap for bandgap (1 nF) External res for bandgap (25 kOhm) Analog ground bandgap Laser driver input from monitor diode Laser driver compensation cap (30 nF) First laser driver output Second laser driver output 3.3 V for AFE pad ring Analog 3.3 V for test buffer Test buffer positive output Test buffer negative output Analog ground test buffer Analog 1.8 V ADC Analog ground ADC Core VSS ground Hardware reset input (pull-up) Test enable signal (active low) Description Pin type analog in analog in analog in analog in VDD VDD analog in analog in analog out analog out VDD analog analog Vss analog in analog analog out analog out VDD VDD analog out analog out VSS VDD VSS VSS in, schmitt, 3.3 V in, 3.3V LQFP144 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56
Focusing actuator control signal output Out, 3.3 V, 4 mA PDM Clock (50% duty cycle) for actuator PDM reference Out, 3.3 V, 2 mA
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Pin description Table 2.
N 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 SPDL SLED1 SLED2 VDD VSS VDD3 TFSR CAV LRCK GPA9 GPA10 GPA11 GPA12 SDO/SPDIF BCLK GPA0 (EINT0) NC NC NC GPA1 (EINT1) GPA2 (EINT2) GPA3 (EINT3) GPA13 GPA4 (EINT4) GPA5 (EINT5)
STA1052
Pin List (continued)
Name Description Spindle motor control signal output PDM SLED motor control signal output1 (stepping/DC) - PDM SLED motor control signal output2 (stepping) -PDM Core VDD 1.8 V Digital pad ring VSS ground Digital pad ring VDD3 3.3 V Pin type Out, 3.3 V, 2 mA Out, 3.3 V, 2 mA Out, 3.3 V, 2 mA VDD VSS VDD3 LQFP144 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 , 2 mA, PU (default off) 76 77 78 79 80 81
Tracking actuator control signal output Out, 3.3 V, 4 mA PDM CAV feedback input Serial L/R clock GPA9 (I2S1_Tx_SCK (SCK1)) GPA10 (I2S1_Tx_WCK (SC12)) GPA11 (I2S1_Tx_SDO (STD1)) GPA12 (I2S1_ref_CK) Serial bit data or SPDIF Digital output Serial bit clock GPIO PA0 (external interrupt 0/timer 0 output 0) Not connected Not connected Not connected GPIO PA1 (external interrupt 1/timer 0 output 1) GPIO PA2 (external interrupt 2/timer 1 output 0) GPIO PA3 (external interrupt 3/timer 1 output1 ) GPIO PA13 (SPDIF Rx) GPIO PA4 (external interrupt 4) GPIO PA5 (external interrupt 5) in, 3.3 V bidir, 3.3 V, 2 mA bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 V, mA, PU (default off) bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 V, 2 mA bidir, 3.3 V, 2 mA bidir, 3.3 V, 2 mA, PU (default off)
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STA1052 Table 2.
N 79 80 81 82 83 84 85 86 87 88 89 90 91
Pin description Pin List (continued)
Name Description GPIO PA6 (external interrupt 6) GPIO PA7 (external interrupt 7) GPIO PA8 (external interrupt 8) GPIO PB0 or serial Flash slave select (external interrupt 9) Digital pad ring VSS ground Digital pad ring VDD3 3.3 V GPIO PB1 or I2C CRQ line (external interrupt 10) GPIO PB2 or I2C I/F clock (external interrupt 11) GPIO PB3 or I2C I/F data (external interrupt 12) GPIO PB4 or serial interface 0 TX or EXTCK_OIF GPIO PB5 or serial interface 0 RX (external interrupt 13) GPIO PB8 or C2PO (EIAJ CP-340) or USB clock line (48 MHz) Core VDD 1.8 V GPIO PB6 or serial interface 1 TX or USB D- line Pin type bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 V, 2 mA, PU (default off) Vss VDD3 bidir, 5 V tol, 2 mA(sink) bidir, 5 V tol, 2 mA(sink) bidir, 5 V tol, 2 mA(sink) bidir, 3.3 V, 2mA, PU (default off) bidir, 3.3V, 2mA, PU (default off) bidir, 3.3V, 2mA, PU (default off) VDD bidir, 3.3 V, 2 mA, PU (default off)(1) USB pad (Full / Low speed ) bidir, 3.3 V, 2 mA, PU (default off)(1) USB pad (Full / Low speed ) in, 3.3V out, 3.3 V, 2 mA in, 3.3 V VDD3 Vss VSSDAC VDDDAC analog out analog in LQFP144 82 83 84 85 86 87 88 89 90 91 92 93 94
GPA6 (EINT6) GPA7 (EINT7) GPA8 (EINT8) GPB0/SFLASH_SS (EINT9) VSS VDD3_Core2 GPB1/I2C_CRQ (EINT10) GPB2/I2C_SCL (EINT11) GPB3/I2C_SDA (EINT12) GPB4/SCI0TX GPB5/SCI0RX (EINT13) GPB8/C2PO/USBCK VDD
92
GPB6/SCI1TX/USBDM
95
93
GPB7/SCI1RX/USBDP (EINT14) JTDI JTDO JTMS VDD3 VSS ADAC_VSSA
GPIO PB7 or serial interface 1 RX or USB D+ line (external interrupt 14) JTAG test data input JTAG test data output JTAG test mode select input Digital pad ring VDD3 3.3 V Digital pad ring VSS ground Audio DAC ground Audio DAC supply 3.3 V Left channel analog output Audio DAC VLO (GND)
96
94 95 96 97 98 99
97 98 99 100 101 102 103 104 105
100 ADAC_VDDA 101 OUTL 102 ADAC_REF2
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Pin description Table 2.
N 103 VCM 104 ADAC_REF1 105 OUTR NC
STA1052
Pin List (continued)
Name Description Common Mode input for audio DAC (1.65 V) Audio DAC VHI (3.3 V) Right channel analog output Not Connected JTAG test clock input JTAG test reset input SDRAM bank sel address 1 SDRAM bank sel address 0 and configuration bit 4 (latched at reset) SDRAM address 11 and configuration bit 3 (latched at reset) SDRAM Address 10 and configuration bit 2 (latched at reset) in, 3.3 V in, schmitt, 3.3 V out, 3.3 V, 4 mA bidir, 3.3 V, 4 mA Pin type analog in analog in analog out LQFP144 106 107 108 109 110 111 112 113
106 JTCK 107 JTRST 108 DRBA1 109 DRBA0/CFG4
110 DRA11/CFG3
bidir, 3.3V, 4mA
114
111 DRA10/CFG2
bidir, 3.3 V, 4 mA
115
112 DRA9/CFG1
SDRAM Address 9 and configuration bit 1 bidir, 3.3 V, 4 mA (latched at reset) SDRAM Address 8 and configuration bit 0 bidir, 3.3 V, 4 mA (latched at reset) SDRAM address 7 SDRAM address 6 SDRAM address 5 Core VDD 1.8 V Digital pad ring VSS ground Digital pad ring VDD3 3.3 V SDRAM address 4 SDRAM address 3 SDRAM address 2 SDRAM address 1 SDRAM address 0 SDRAM write control SDRAM col address sel SDRAM row address sel SDRAM CLK enable SDRAM CLK out, 3.3 V, 4 mA out, 3.3 V, 4 mA out, 3.3 V, 4 mA VDD VSS VDD3 out, 3.3 V, 4 mA out, 3.3 V, 4 mA out, 3.3 V, 4 mA out, 3.3 V, 4 mA out, 3.3 V, 4 mA out, 3.3 V, 4 mA out, 3.3 V, 4 mA out, 3.3 V, 4 mA out, 3.3 V, 4 mA out, 3.3 V, 4 mA
116
113 DRA8/CFG0 114 DRA7 115 DRA6 116 DRA5 117 VDD 118 VSS 119 VDD3 120 DRA4 121 DRA3 122 DRA2 123 DRA1 124 DRA0 125 DRWR 126 DRCAS 127 DRRAS 128 DRCLKE 129 DRCLK
117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133
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STA1052 Table 2.
N 130 VSS 131 VDD3_Core1 132 GPC15 (DRD15) 133 GPC14 (DRD14) 134 GPC13 (DRD13) 135 GPC12 (DRD12) 136 GPB9 137 GPB10 138 GPB11 139 GPC11 (DRD11) 140 GPC10 (DRD10)
Pin description Pin List (continued)
Name Description Digital pad ring VSS ground Digital pad ring VDD3 3.3 V GPIO PC15 (SDRAM Data 15) GPIO PC14 (SDRAM Data 14) GPIO PC13 (SDRAM Data 13) GPIO PC12 (SDRAM Data 12) GPB9 (I2S1_Rx_SCK (SC10)) GPB10 (I2S1_Rx_WCK (SC11)) GPB11 (I2S1_Rx_SDI (SRD1)) GPIO PC11 (SDRAM Data 11) GPIO PC10 (SDRAM Data 10) VSS VDD3 bidir, 3.3 V, 4 mA bidir, 3.3 V, 4 mA bidir, 3.3 V, 4 mA bidir, 3.3 V, 4 mA bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3V, 2mA, PU (default off) bidir, 3.3 V, 2 mA, PU (default off) bidir, 3.3 V, 4 mA bidir, 3.3V , 4 mA Pin type LQFP144 134 135 136 137 138 139 140 141 142 143 144
1. The specifications in USB mode are as per USB specifications for low and full speed interface.
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Package information
STA1052
4
Package information
In order to meet environmental requirements, ST (also) offers these devices in ECOPACK(R) packages. ECOPACK(R) packages are lead-free. The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. Figure 3. LQFP144 (20x20x1.4mm) mechanical data and package dimensions
mm DIM. MIN. A A1 A2 b c D D1 D3 E E1 E3 e L L1 k ccc 0.450 0.050 1.350 0.170 0.090 1.400 0.220 TYP. MAX. 1.600 0.150 0.0020 MIN. TYP. MAX. 0.0630 0.0059 inch
OUTLINE AND MECHANICAL DATA
1.450 0.0531 0.0551 0.0571 0.270 0.0067 0.0087 0.0106 0.200 0.0035 0.0079
21.800 22.000 22.200 0.8583 0.8661 0.8740 19.800 20.000 20.200 0.7795 0.7874 0.7953 17.500 0.6890
21.800 22.000 22.200 0.8583 0.8661 0.8740 19.800 20.000 20.200 0.7795 0.7874 0.7953 17.500 0.500 0.600 1.000 0.6890 0.0197 0.750 0.0177 0.0236 0.0295 0.0394
0(min.), 3.5(typ.), 7(max.) 0.080 0.0031
LQFP144 (20x20x1.40mm) Low profile plastic Quad Flat Package
Note 1: Exact shape of each corner is optional.
0099183 C
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STA1052
Revision history
5
Revision history
Table 3.
Date 12-Mar-2008
Document revision history
Revision 1 Initial release. Changes
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STA1052
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